Traditional column redundancy schemes for a non-volatile memory provide the non-volatile memory chip with a page-buffer (SRAM) and a multiplexer. In the first scheme, a page-buffer holds data while column redundancy is being processed. In the second scheme, control logic multiplexes data from a redundancy bitline when a column counter addresses a bitline with defective memory cells. Both of these column redundancy schemes require significant chip area and processing time, especially when the implementations use high voltage devices or are located close to the memory core.
A problem with present serial high-density FLASH memory controller logic chips is under-utilization of the controller logic chip functions when serial data is clocked into or out of the FLASH memory chip. During these times, while a user has control of the system clock and data, not much is happening concurrently in the controller logic chip aside from the opening of data paths to allow data to flow to or from a user. Replacement of redundant data, if not done during this data-clocking period, would have to be done before the next data-clocking period. The resulting increases in latency and chip area needed for the required specialized redundancy logic become more problematic as demand grows for faster serial memories with higher densities.